Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
As semiconductor technology advances, 3D memory devices, such as 3D NAND memory devices, keep scaling more oxide/nitride (ON) layers to improve the area utilization of wafers. In some existing 3D NAND memory devices, source selective gates are located at bottom of alternating layer stack, and drain selective gates are located at top of the alternating layer stack. A gate oxide layer of the drain selective gates generally includes a silicon nitride layer as a charge trap layer. Thus, in operations of the existing 3D NAND memory devices, the drain selective gates inevitably storage and release charges, which can easily cause a threshold voltage drift, resulting a current change or even a current leakage in the vertical channels. The problems may get worse after multiple repeated reading and writing operations, and eventually cause a read failure of the existing 3D NAND memory devices.